Learning ARM assembly (and exploits) [Laurent Steff]
jeudi 27 avril 2023
« What better timing that the new release of QEMU, which enable us playing with ARM and RISC-V without dedicated hardware, to learn more ARM assembly ? This pretty clear and comprehensive website will guide you from creating your environment, writing assembly to more advanced security related topics.  »
[ARM, processeur, assembly, security]
NASA selects RISC-V for its future flight processor [Laurent Steff]
jeudi 29 septembre 2022
« From the article: "Besides the performance, one major reason that NASA may be interested in SiFive’s cores is that they are RISC-V offerings"  »
[processeur, embedded, open_source]
Intel and AMD new approaches on interrupt and exception handling discussed [Laurent Steff]
mercredi 7 avril 2021
« Current x86-64 processors have legacy oddities regarding interrupt and exceptions handling due to design in place since almost 40 years ago. On this Linux Reviews article, proposal of both Intel and AMD are reviewed, including comments of Linus Torwalds.  »
[processeur, linux, Linus_Torvalds, kernel]
What happens inside Eigen, on a simple example [Laurent Steff]
mardi 2 mars 2021
« The journey of what happens from a simple Eigen Vector addition in C++ to assembly. From high level like Template MetaProgramming, Curiously Recurring Template Pattern or traits, to low level like alignment and Streaming SIMD Extensions (SSE) intrinsic functions.  »
[c++, design_pattern, processeur]
Intel x86s hide another CPU that can take over your machine (you can't audit it) [Romain]
vendredi 17 juin 2016
« Une interface de gestion opaque présente sur les plate-formes intel. »
[sécurité, processeur]